1. Field of the Invention
The invention relates to computer systems using dynamic random access memories and more particularly to computer systems using page mode operation dynamic random access memories.
2. Discussion of the Related Art
Personal computer systems having been getting faster and more powerful at a rapid rate and yet more speed and power is always being demanded. To this end 32 bit microprocessors with even higher clock rates have been employed. However, processor speed has readily outstripped the speed of economical memory devices. To run many current processors without wait states requires 25 nsec memories. These memory devices are prohibitively expensive to be used as the main system memory, so two avenues are available.
The first possibility is to use the fastest, economically feasible memory devices in the main system memory and just bear the performance loss, hoping that other considerations are more important. Operating the memory devices in page mode where only a column address needs to be supplied if the row address is the same as the previous access, referred to as a page hit, improves the situation, but generally not enough to meet demands. The second avenue available is the use of a cache memory system which uses a small amount of high speed, zero wait state memory which contains a copy of portions of the data stored in the main memory. By properly sizing and organizing the cache memory, in excess of 90% of the memory accesses can be run out of the cache memory, this percentage being referred to as the hit ratio. The slower main memory is accessed only when the data is not in the cache, which is called a miss operation. The use of a cache memory system allows more economical memory devices to be used for main memory because the speed factor is not as critical because of the lower percentage of accesses to the main memory.
Even the improvement provided by using cache memory has not been sufficient to meet performance demands. The cache memory systems used in personal computers generally resulted in the location of the main memory on a bus separated from the processor, which resulted in delays of operation relative to a system not having this additional bus when access had to be made to the main memory in cache miss instances. Page mode main memory device operation has been combined with a cache memory system to improve the performance during cache miss cycles, but this still resulted in the inclusion of wait states in accesses to main memory, generally two wait states in page hit cases.